I. Field of the Invention
This invention relates to the field of frequency dividers, and more specifically, programmable frequency dividers capable of a 50% duty cycle for odd and even integer divide ratios.
II. Background of the Invention
In order to provide greater flexibility in frequency planning, a competitive integrated circuit (IC)-based high frequency transceiver requires fully programmable frequency division. For example, in the receiver portion of the transceiver, a local oscillator (LO) frequency is typically a multiple of a certain reference frequency, and a programmable frequency divider is included in a phase locked loop (PLL) to generate the correct LO frequency. In the transmitter portion of the transceiver, a programmable frequency divider is typically included in the translational loop to generate the necessary radio (RF) or intermediate frequency (IF).
Conventional approaches employing counters or cascaded flip-flops may not be acceptable in every situation because they are incapable of producing an output having a 50% duty cycle, no matter what the integer divide ratio, or are incapable of doing so at odd integer divide ratios. FIG. 1A illustrates a clock signal, and FIG. 1B illustrates an output signal representing a division ratio of 3 obtained from a conventional frequency divider. As can be seen, the duty cycle of the signal, representing the fraction of a period the signal is in a high state, deviates substantially from 50%. A 50% duty cycle in the output signal is preferred because such signals lack even harmonics. Even harmonics in the output signal are sought to be avoided because they may cause spurious effects in many high frequency applications. For example, in integrated circuits, the introduction of even harmonics defeats the purpose of using purely differential mode signals.
Consequently, there is a need for a programmable frequency divider that is capable of producing a 50% duty cycle in the output signal at all integer divide ratios, both odd and even.